The VHDL Programming Training for FPGA, meticulously structured for professionals and enthusiasts eager to harness the full potential of FPGA design. This course offers a detailed insight into VHDL syntax and coding styles pivotal to logic design, coupled with hands-on sessions on writing robust VHDL RTL hardware designs. By incorporating good coding practices, learners will comprehend the synthesizable subset of VHDL, shedding light on potential pitfalls and problematic coding areas.

Furthermore, participants will explore the dynamic world of standard VHDL packages, including std_logic_1164 and numeric_std, mastering types, overloading, and conversion functions. The training doesn't stop at the basics; delve into advanced testbench writing using TEXTIO, and craft transaction-based testbenches through subprograms. By the course's conclusion, attendees will be adept at leveraging VHDL simulation and synthesis tools, ensuring an elevated competency in FPGA design and VHDL programming.

Certificate

All participants will receive a Certificate of Completion from Tertiary Courses after achieved at least 75% attendance.

Funding and Grant

HRD Corp Claimable Course for Employers Registered with HRD Corp

Course Code: M422

Day 1

FPGA Design FLOW

• Motivation

Topic 1 : Introduction to VHDL

• Library & Packages

• Entity/Modes

• Architecture

Topic 2: VHDL Data Types

• Language Elements

• Identifiers

• Literals

• Types

• Conversion (Advance)

• Object Types

• TEXTIO

Topic 3: Operators

• Logical Operator

• Relational Operators

• Arithmetic Operator

• Resize function

• Shift Operators

• Multiplying Operators

• Miscellaneous Operators

Topic 4: Concurrent Statements

• Aggregates

• Drivers

• Concurrent Statement 

• Component Instantiation

• Block Statement

• Generate Statement

Topic 5: Sequential Statements

• Process statement / Sensitivity List

• Wait statement

• IF statement

• Case statement

• Loop

• Define Range

• Variables

• Variables Vs Signals

Topic 6: Configuration

• Generic

• Operator Overloading

• Attributes

Topic 7: Lab Exercise

• Combinational Logic

Day 2

Topic 8: State Machine

• Mealy 

• Moore

Topic 9: Simulation

• Steps of simulation / Simulation Deltas

• Inertia Delay / Transport delay

• Test bench

Topic 10: Lab Activities

• Design Entry

• Writing VHDL code 

• Test bench 

• Simulating VHDL code with Vivado (Xilinx)

• Synthesize the code